Conventionally, internal transfer of data has been performed in a storage device or the like. In recent years, with the demand for improvement in the data transfer amount or data transfer speed, there has been widely used a technique of transferring data at high speed by non-handshake communication. In such non-handshake communication, delivery of data is not assured, so that a technique of assuring delivery of data is desired.
As a technique related to the above-mentioned delivery assurance, to verify writing of data into a memory by DMA (direct memory access), there has been proposed a technique of counting the number of data items using a bus monitor (e.g. see Japanese Laid-Open Patent Publication No. 2004-355430).
Further, for a serial data transfer system, there has also been proposed a technique of checking a data error by adding a CRC code to data (e.g. see Japanese Laid-Open Patent Publication No. 10-290270).
Further, for a delivery type data transfer system, there has been proposed a technique in which a target device monitors data transfer to another target device via a bus, and captures the transferred data in the target device itself as well (e.g. see Japanese Laid-Open Patent Publication No. 09-251439).
Furthermore, as a technique of monitoring a bus signal, there has been proposed a technique in which a CPU circuit is used which is capable of monitoring various types of events generated on a communication channel is used, and if an event of a specific type is generated, the CPU circuit is reconfigured (e.g. see Japanese PCT Application Translation Publication No. 2005-501337).
However, in the internal transfer of data, data to be transferred is often transferred after being divided into a plurality of data items, and hence any of the conventional techniques disclosed as above does not enable confirmation of delivery of all data items without fail, with high assurance and with simple configuration.